XIP1183H from Xiphera is a high-speed  Intellectual Property (IP) core implementing the Advanced Encryption Standard (AES) with 256-bit long key in XTS mode.
XTS is a mode of operation for a block cipher that is used primarily for protecting the confidentiality of data at rest. Consequently, AES-XTS is widely used for encrypting the contents of hard drives and other storage devices.
AES-XTS is a tweakable block cipher, and as it instantiates the underlying AES block cipher twice, the key material for AES-XTS is twice longer than for the constituent individual AES block ciphers.
The encrypted data depends not only on the plaintext and encryption key, but also on the logical address of the data on the storage device. This means that identical plaintexts get encrypted differently at different logical addresses.
XIP1183H has been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of XIP1183H does not rely on any FPGA manufacturer-specific features.
AES256-XTS works by first encrypting the tweak value  with an AES block. The encrypted tweak value is then multiplied  with a value derived from the Block Sequence Number  of the 128-bit block inside the data unit.
The resulting value is then used in an Exlusive OR (XOR) operation both at the input and output of another AES block (“datapath AES”), which uses a different 256-bit key from the AES block responsible for encrypting the tweak value. The default configuration of XIP1183H encrypts/decrypts an entire disk sector in burst mode.
Decryption is an identical operation to encryption, with the exception that the datapath AES operates in the decryption mode.
For more technical and commercial details, including FPGA resources & peak performance as well as ordering instructions, open the full product brief in PDF. Contact us by sending and email to , and we’ll get back to you as soon as possible.
Figure 1: Internal high-level block diagram of XIP1183H.
 Xiphera’s high-speed (denoted by ’H’ at the end of the ordering code) IP cores are designed to maximize the achievable FPGA performance.
 The AES S-boxes can be implemented either in FPGA logic or internal memory blocks depending on the
 The default sector size is parameterizable.
 The AES-XTS standard defines the tweak as a 128-bit value used to represent the logical position of the data being encrypted or decrypted, which in practice is most often the address of an individual sector on the storage media.
 The multiplication is performed in Galois field GF(2128) defined by the polynomial x128 + x7 + x2 + x + 1.
 The default configuration of XIP1183H uses a 4kB sector size, but this can be easily parameterized.
Xiphera Ltd © 2022