AES-CTR
Xiphera’s portfolio of symmetric encryption algorithms provides uncompromised data encryption.
About the product
Advanced Encryption Standard (AES) is the predominant block cipher technique for symmetric encryption, serving as the primary encryption algorithm for protecting data communication and storage. Xiphera’s Symmetric Encryption portfolio offers a wide range of IP cores for AES algorithms optimised for optimal resource usage and performance.
Xiphera’s AES-CTR IP cores implement the AES in Counter mode, a method that effectively turns a block cipher into a stream cipher while providing multiple advantages from an implementation perspective.
Xiphera’s high-speed AES-CTR (XIP1103H) is designed for seamless integration within FPGA- and ASIC-based designs, following a vendor-agnostic approach where the IP core functionalities are independent of any manufacturer-specific features. The IP core is validated under the CAVP validation program from the U.S. NIST (National Institute of Standards and Technology).
Key features
- Moderate resource requirements: The high-speed AES-CTR does not require any multipliers or DSPBlocks in a typical FPGA implementation.
- Performance: Despite its moderate size, the IP core achieves a throughput in the tens of Gbps range.
- Standard Compliance: Xiphera’s AES-CTR is fully compliant with both the Advanced Encryption Algorithm standard, as well as with the Counter Mode standard.
- 128-bit and 256-bit Interfaces ease the integration of the high-speed AES-CTR with other FPGA logic and/or control software.
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Partner collaborations
We are proud partners with leading global as well as innovative growing FPGA companies. We offer a selection of our cryptographic IP cores for our technology partners. Visit our partner pages to learn more about our MACsec offering on our partner portfolios.