Xiphera’s portfolio of symmetric encryption algorithms provides uncompromised data encryption.

About the product

Ascon is a lightweight, sponge-based, algorithm that can perform three cryptographic primitives: authenticated encryption with associated data (AEAD), hashing, and extendable output function (XOF). Xiphera offers the Ascon IP core (XIP2201B) supporting a lightweight cryptographic suite for AEAD and hashing. The intention with Ascon is not to replace the already widely used AES-GCM and SHA-3 algorithms, but rather to offer a smaller alternative for devices with limited resources. Hence, the Ascon IP core is especially useful for small devices used in Industrial IoT.

AEAD is a cryptographic scheme where one can encrypt as well as authenticate data, preserving privacy and integrity of the sent data. Associated data refers to data that is not encrypted but is also authenticated. Hashing is a one-way input function mapping messages to fixed length hashes such that a hash cannot be inverted back to the message. XOFs are like hashes but they allow for variable length output.

Xiphera’s IP cores are designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of our Ascon IP core does not rely on any FPGA manufacturer-specific features.

Key features

  1. Small Resource Requirements: The Ascon IP core requires less resources and yet provide optimised performance. You can download the product brief to get detailed performance numbers.
  2. Versatile Algorithm Support: The Ascon IP core supports ASCON-128/128a/80pq/Hash/Hasha as well as XOF and XOFa.
  3. Secure Architecture: The execution time of our Ascon IP core is independent of the input values and, consequently, provides full protection against timing-based side-channel attacks.
  4. Standard Compliance: The Ascon IP core is compliant with Ascon specification 1.2 (31.05.2021) which is the version that was selected to be standardized by NIST. Xiphera commits to update XIP2201B when the standardization proceeds to newer versions.
  5. Easy Integration: The 64-bit interface of our Ascon IP core supports easy integration to various systems
Internal high-level block diagram of balanced Ascon IP core (XIP2201B).
Internal high-level block diagram of the balanced Ascon IP core.

For more details, including FPGA resources & peak performance as well as ordering instructions, open the full product briefs in PDF. Contact us here, and we’ll get back to you as soon as possible.

Interested to learn more about the technical details and performance numbers for ASIC application? Register for the ASIC-specific product brief here.