Xiphera’s portfolio of symmetric encryption algorithms provides uncompromised data encryption.

About the product

Advanced Encryption Standard, AES, is the most widely used block cipher (symmetric encryption) and the primary encryption algorithm for protecting data communication and storage. AES functions by encrypting a 128-bit block of data using an either 128, 192, or 256-bit key. AES is a symmetric encryption algorithm, where the same key is used for both encrypting and decrypting a message.

Xiphera provides a well-rounded Intellectual Property (IP) core that implements the Advanced Encryption Standard (AES) with a 256-bit key in XTS mode. AES-XTS is a block-based encryption method primarily employed to secure data while it is stored. As a result, AES-XTS is extensively utilized to encrypt data on hard drives and other storage devices. All our IP cores are engineered to seamlessly integrate with FPGA and ASIC-based projects, following a vendor-independent design approach, and their functionality is independent of any manufacturer-specific FPGA features.

We offer two versions of AES-XTS (AES256-XTS) IP core, a balanced and a high-speed core.

  1. Balanced Advanced Encryption Standard (256-bit key), XTS mode IP Core (XIP1183B)
  2. High-speed Advanced Encryption Standard (256-bit key), XTS mode IP Core (XIP1183H)

Key features

  1. Standard Compliance: AES256-XTS is compliant with both the Advanced Encryption Algorithm (AES) standard and the XTS standard.
  2. Optional Ciphertext stealing supported in both versions of our AES256-XTS IP core.
  3. Increased Performance can be achieved by parallel instantiations of our AES256-XTS IP core.
Internal high-level block diagram of the high-speed AES-XTS IP core (XIP1183H).
Internal high-level block diagram of the high-speed AES-XTS IP core.

For more details, including FPGA resources & peak performance as well as ordering instructions, open the full product briefs in PDF. Contact us here, and we’ll get back to you as soon as possible.

Interested to learn more about the technical details and performance numbers for ASIC application? Register for the ASIC-specific product brief of the high-speed AES256-XTS IP core here.