Versatile AES

Xiphera’s portfolio of symmetric encryption algorithms provides uncompromised data encryption.

About the product

Advanced Encryption Standard, AES, is the most widely used block cipher (symmetric encryption) and the primary encryption algorithm for protecting data communication and storage. AES encrypts a 128-bit data block with a 128, 192, or 256-bit key. It’s a symmetric encryption method, using the same key for encryption and decryption. AES must be used in a secure mode of operation, like Cipher Block Chaining (CBC) or Counter (CTR). Certain modes of operation such as Galois Counter Mode (GCM) also provide assurances of data authenticity in addition to data confidentiality.

Xiphera’s balanced Versatile AES-256 IP core supports AES with a 256-bit key in five selectable modes: Electronic Codebook (ECB), Cipher Block Chaining (CBC), Cipher Feedback (CFB), Output Feedback (OFB), and Counter (CTR). These modes (CBC, CFB, OFB, and CTR) all ensure data confidentiality and are widely used in security designs and cryptographic protocols.

Additionally, all Xiphera’s IP cores are designed for straightforward integration into FPGA and ASIC-based projects, following a vendor-independent approach that doesn’t rely on specific FPGA manufacturer features. It is worth noting that our Versatile AES IP core has obtained CAVP validation batch.

Key features

  1. Moderate resource requirements: The entire IP core requires moderate resources and does not require any multipliers or DSPBlocks4.
  2. Performance: Versatile AES-256 IP core achieves an impressive throughput in the Gbps range.
  3. Standard Compliance: Versatile AES-256 IP core is fully compliant with both the Advanced Encryption Algorithm (AES) standard, as well as with the ECB, CBC, CFB, OFB, and CTR modes of operation.
  4. Versatility: The key, initialization vector (IV), and the mode of operation can dynamically be updated for every 128-bit data block.
Internal high-level block diagram of the balanced Versatile AES-256 IP core (XIP1123B).
Internal high-level block diagram of the balanced Versatile AES-256 IP core.

For more details, including FPGA resources & peak performance as well as ordering instructions, open the full product briefs in PDF. Contact us here, and we’ll get back to you as soon as possible.

Interested to learn more about the technical details and performance numbers for ASIC application? Register for the ASIC-specific product brief here.

Partner collaborations

We are proud partners with leading global as well as innovative growing FPGA companies. We offer a selection of our cryptographic IP cores for our technology partners. Visit our partner pages to learn more about our Versatile AES offering for our partners.