True Random Number Generation (TRNG)

Xiphera offers randomness with industry standard-compliant True Random Number Generators (TRNG) and Pseudorandom Number Generators (PRNG).

About the product

Xiphera has designed a hardware-based TRNG IP core (XIP8001B) with an entropy source. The FPGA independent and ASIC compatible TRNG IP core includes the online health tests and construction described in NIST SP 800-90B, and has a standard compliant AES-CBC-MAC-based entropy extractor.

Our proprietary TRNG IP core is employed in other Xiphera products such as TLS 1.3 and can also seamlessly integrate with Xiphera’s MACsec. The robustness of Xiphera’s TRNG IP core is verified with multiple FPGA families from Intel, AMD, Lattice Semiconductor, and Microchip, passing all the popular test suites including dieharder, NIST SP800-22 and SP800-90B.

Key features

  1. Compact Size: The IP core is designed to be compact in size, and you can find detailed information about its resource requirements for various FPGAs in the product brief.
  2. Autonomous Operation: The entropy source used by our TRNG IP core functions independently from the rest of the FPGA logic; for example, no FPGA internal clock signals are required for the entropy source to function.
  3. Parameterisability: The TRNG IP core has a number of parameterisable features, including the width of the dout output, the sizes (width and depth) of the internal buffers, and the threshold values for the health tests.
  4. Security Features: The TRNG IP core has a number of additional security features, including a zeroize function to erase (set to ’0’) all the bits in the internal buffer.
  5. Standard Compliance: The TRNG IP core has been designed to comply with NIST SP 800-90B, thus making its use in a crypto module targeting a FIPS 140-3 certification possible.
  6. Passing Statistical Tests: The output of the entropy source in our TRNG IP core passes PractRand, gjrand, TestU01, the NIST SP 800-22 statistical test suite, and the dieharder test suite.
Internal high-level block diagram of the balanced TRNG IP core (XIP8001B).
Internal high-level block diagram of the balanced TRNG IP core.

For more details, including FPGA resources & peak performance as well as ordering instructions, open the full product briefs in PDF. Contact us here, and we’ll get back to you as soon as possible.

Interested to learn more about the technical details and performance numbers for ASIC application? Register for the ASIC-specific product brief here.

Partner collaborations

We are proud partners with leading global as well as innovative growing FPGA companies. We offer a selection of our cryptographic IP cores for our technology partners. Visit our partner pages to learn more about our TRNG offering for our partners.