Xiphera’s cryptographic Security Protocol portfolio secures point-to-point communication as well as server-client connections over the Internet.

About the product

IPsec (Internet Protocol Security) is a widely accepted and adopted security protocol, ensuring secure communication over the Internet. Xiphera’s IPsec core implements ESP (Encapsulating Security Payload) frame processing in the IPsec protocol using Xiphera’s own AES256-GCM. The IPsec protocol secures the communication traffic on the Layer 3 of the OSI model by assuring that a received frame has been sent by a transmitting station that claimed to send it, and by encrypting the contents.

Xiphera’s scalable extreme-speed IPsec IP core (XIP7013E) is best suited for traffic on links from 10 Gbps to 200 Gbit/s links with high-end FPGAs or ASICs. The IP core has been designed for easy integration for FPGAs and ASICs in a vendor-agnostic design methodology.

Key features

  1. Performance: The extreme-speed IPsec achieves a throughput exceeding 100 Gbps range in modern high-end FPGAs and ASICs. The IP core does not require any extra interpacket gap cycles even when it processes short packets.
  2. Standard Compliance: The scalable IPsec is compliant with RFC4303. The cipher suite (AES256- GCM) is fully compliant with the Advanced Encryption Algorithm (AES) standard, as well as with the Galois Counter Mode (GCM) standard.
  3. Easy Interfacing: The extreme-speed IPsec uses a streaming interface for payload data and side-channel signalling for the required ESP frame parameters.
Internal high-level block diagram of Xiphera's extreme-speed IPsec IP core (XIP7013E).
Internal high-level block diagram of Xiphera's extreme-speed IPsec IP core.

For more details, including FPGA resources & peak performance as well as ordering instructions, open the full product briefs in PDF. Contact us here, and we’ll get back to you as soon as possible.