Hardware-based security for high-level protection.

XIP3030C: SHA-3

A Compact Versatile Core for SHA-3-224/256/384/512 and (c)SHAKE-128/256


XIP3030C is a compact IP core designed for versatile support of all variants of the SHA-3 hash function and related extendable-output function SHAKE as well as the SHA-3 derived function cSHAKE and its variants KMAC, TupleHash and ParallelHash (including their arbitrary-length output variants). SHA-3 and SHAKE are defined in the NIST (National Institute of Standards and Technology) standard FIPS PUB 202 and cSHAKE, KMAC, TupleHash and ParallelHash are specified in NIST Special Publication 800-185.

Because of the versatile algorithm support, XIP3030C can be used in various applications that require SHA-3 hashing or other supported SHA-3 based functionalities. XIP3030C consumes only small amounts of FPGA resources that allows it to be used even in settings where resources are scarce. SHA-3 plays a central role also in post-quantum cryptography schemes. The design is device-agnostic and fully compliant with various FPGA platforms. XIP3030C offers high level of implementation security and is fully protected against timing attacks as its execution time does not depend on the values of the inputs.

The interface of XIP3030C is pin-wise compatible with XIP3030H, the high-speed versatile SHA-3 core with the same functionalities. The only differences are in performance (latency) and resource requirements. XIP3030C has been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of XIP3030C does not rely on any FPGA manufacturer-specific features.

Key features

  • Minimal Resource Requirements: XIP3030C requires 673 ALMs with Intel Cyclone ® V SX SoC or 978 6-input LUTs with Xilinx Artix-7 ® and use only some internal memory blocks in a typical FPGA implementation.
  • Versatile Algorithm Support: XIP3030C supports SHA-3-224/256/384/512, SHAKE-128/256, and cSHAKE-128/256.
  • Secure Architecture: The execution time of XIP3030C is independent of the input values and, consequently, provides full protection against timing-based side-channel attacks.
  • Standard Compliance: XIP3030C is compliant with FIPS 202 and SP 800-185. XIP3030C can be used as a part of numerous systems and protocols that require SHA-3 or its derivatives.
  • Easy Integration: The 64-bit interface of XIP3030C supports easy integration to various systems.


The main functionality of XIP3030C is to calculate a SHA-3 message digest (also commonly known as a hash value). SHA-3 is a family of hash functions that NIST has standardized in FIPS PUB 202 in August 2015.

In addition to basic hash functions SHA-3-224/256/384/512 with outputs (hashes) of different predefined lengths, XIP3030C supports SHAKE-128 and SHAKE-256. They are extendable-output functions (XOFs), and they allow a user to query arbitrary-length output data from the functions while maintaining the security levels of 128 and 256 bits, respectively. Additionally, XIP3030C supports also NIST Special Publication 800-185 by supporting cSHAKE-128 and cSHAKE-256 XOFs.

The XIP3030C is optimised for low resource usage and compact footprint.

For more technical and commercial details, including FPGA resources & peak performance as well as ordering instructions, open the full product brief in PDF. Contact us by sending and email to email_career.png, and we’ll get back to you as soon as possible.

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Block diagram

Internal high-level block diagram of XIP3030C

Internal high-level block diagram of XIP3030C.

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