Hardware-based security for high-level protection.

XIP1113H: AES256-GCM

Advanced Encryption Standard (256-bit key), Galois Counter Mode IP Core


XIP1113H from Xiphera is a high-throughpout Intellectual Property (IP) core implementing the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM). AES-GCM is a widely used cryptographic algorithm for Authenticated Enryption with Associated Data (AEAD) purposes, as it provides both data confidentiality and authenticity.

XIP1113H has been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of XIP1113H does not rely on any FPGA manufacturer-specific features.

Key features

  • Moderate resource requirements: The entire XIP1113H requires approximately 21700 Adaptive Lookup Modules (ALMs) (Intel® Cyclone® V), and does not require any multipliers, DSPBlocks or internal memory in a typical FPGA implementation.
  • Optimized Implementation utilizing unrolling, pipelining, optimized AES S-box design, and GMAC calculation based on pipelined Karatsuba multipliers enable extremely high performance.
  • Performance: XIP1113H achieves a throughput in the tens of Gbps range [1], for example 65+ Gbps in Xilinx® UltraScale+™ MPSoC.
  • Standard Compliance: XIP1113H is fully compliant with both the Advanced Encryption Algorithm (AES) standard, as well as with the Galois Counter Mode (GCM) standard.
  • Test Vector Compliance: XIP1113H passes all test vectors specified in MACsec GCM-AES Test Vectors.
  • 128-bit and 256-bit Interfaces ease the integration of XIP1113H with other high-speed FPGA logic.


The main functionality of XIP1113H depends on the mode of operation. When XIP1113H operates in the encryption and authentication tag calculation mode, it encrypts the incoming plaintext blocks into ciphertext blocks, and in addition to this also calculates a 128 bits long authentication tag from both the incoming plaintext and associated data.

When XIP1113H operates in the decryption and tag validity cheching mode, it decrypts the incoming ciphertext blocks into plaintext blocks, and validates the received authentication tag value by calculating the tag from the incoming ciphertext and associated data blocks and comparing the resulting tag value with the received tag value. As defined by the GCM mode of operation, associated data is included in the authentication tag calculation.

XIP1113H can also operate with zero-length associated data, meaning that XIP1113H treats all signals on the input data_in as plaintext to be encrypted or as ciphertext to be decrypted. XIP1113H can also operate with zero-length plaintext or ciphertext, in which case it acts only as an authenticator or authentication validity checker.

XIP1113H outputs first the associated data, followed by encrypted plaintext or decrypted ciphertext (depending on the mode of operation), and as the last output the tag value and associated status signals.

For more technical and commercial details, including FPGA resources & peak performance as well as ordering instructions, open the full product brief in PDF. Contact us by sending and email to email_career.png, and we’ll get back to you as soon as possible.

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Block diagram

Figure 1: Internal high-level block diagram of XIP1113H

Figure 1: Internal high-level block diagram of XIP1113H.


[1] As is typical for AEAD algorithms, the highest throughput is achieved for long messages.

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