Hardware-based security for high-level protection.

XIP1113B: AES256-GCM

Advanced Encryption Standard (256-bit key), Galois Counter Mode IP Core


XIP1113B from Xiphera is a balanced Intellectual Property (IP) core implementing the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM). AES-GCM is a widely used cryptographic algorithm for Authenticated Enryption with Associated Data (AEAD) purposes, as it provides both data confidentiality and authenticity.

XIP1113B has been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of XIP1113B does not rely on any FPGA manufacturer-specific features.

Key features

  • Compact resource requirements: The entire XIP1113B requires approximately 2800 Adaptive Lookup Modules (ALMs) (Intel® Cyclone® V), and does not require any multipliers, DSPBlocks or internal memory [1] in a typical FPGA implementation.
  • Performance: Despite its compact size, XIP1113B achieves a throughput in the Gbps range [2], for example 2.0 Gbps in Xilinx® Artix® -7 family.
  • Standard Compliance: XIP1113B is fully compliant with both the Advanced Encryption Algorithm (AES) standard, as well as with the Galois Counter Mode (GCM) standard.
  • Standard Compliance: XIP1113H is fully compliant with both the Advanced Encryption Algorithm (AES) standard, as well as with the Galois Counter Mode (GCM) standard.
  • Test Vector Compliance: XIP1113B passes all test vectors specified in MACsec GCM-AES Test Vectors.
  • 32-bit FIFO Interfaces [3] ease the integration of XIP1113B with other FPGA logic and/or control software.


The main functionality of XIP1113B depends on the mode of operation. When XIP1113B operates in the encryption and authentication tag calculation mode, it encrypts the incoming plaintext blocks into ciphertext blocks, and in addition to this also calculates a 128 bits long authentication tag from both the incoming plaintext and associated data. When XIP1113B operates in the decryption and tag validity cheching mode, it decrypts the incoming ciphertext blocks into plaintext blocks, and validates the received authentication tag value by calculating the tag from the incoming ciphertext and associated data blocks and comparing the resulting tag value with the received tag value. As defined by the GCM mode of operation, associated data is included in the authentication tag calculation.

XIP1113B can also operate with zero-length associated data, meaning that XIP1113B treats all signals on the input data_in as plaintext to be encrypted or as ciphertext to be decrypted. XIP1113B can also operate with zero-length plaintext or ciphertext, in which case it acts only as an authenticator or authentication validity checker.

XIP1113B outputs first the associated data, followed by encrypted plaintext or decrypted ciphertext (depending on the mode of operation), and as the last output the tag value and associated status signals.

For more technical and commercial details, including FPGA resources & peak performance as well as ordering instructions, open the full product brief in PDF. Contact us by sending and email to email_career.png, and we’ll get back to you as soon as possible.

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Block diagram

Figure 1: Internal high-level block diagram of XIP1113B

Figure 1: Internal high-level block diagram of XIP1113B.


[1] The parameterizable input and output FIFOs may optionally be instantiated with internal memory blocks, but the actual XIP1113B kernel requires only logic resources.

[2] As is typical for AEAD algorithms, the highest throughput is achieved for long messages.

[3] XIP1113B is also available with 128-bits long interfaces, please contact email_career.png for details.

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