Xiphera extends its Transport Layer Security (TLS) product family with new client and server IP cores for FPGA and ASIC circuits, introducing TLS 1.3 server side functionalities and wider feature coverage of TLS 1.3.
TLS is used for securing communication from eavesdropping or manipulation in a large variety of different applications, including secure web browsing as well as machine-to-machine communication protocols. The TLS protocol is based on symmetric and asymmetric cryptography and digital certificates.
High performance with first-grade security
Xiphera’s TLS product family implements both end-points of a TLS 1.3 session in a hardware-only approach. The entire TLS stack, including TLS handshake and related key management, is implemented inside an IP core, the session keys being never visible outside the core. Xiphera TLS products provide throughputs from a few Gbps up to several tens of Gbps. Despite the rich feature set, Xiphera’s TLS products are compact in size and can be used even in resource constrained devices.
“The extension of our TLS offering allows our customers to have more feature-rich TLS solutions for both client and server ends of TLS.” says Kimmo Järvinen, Co-founder and CTO of Xiphera. “Xiphera’s TLS cores combine high performance with first-grade security thanks to the isolation of all cryptographic computations and session key management from the rest of the system.”