Hardware-based security for high-level protection.

XIP8001B: TRNG

True Random Number Generator IP Core


Introduction

XIP8001B from Xiphera is a True Random Number Generator (TRNG) Intellectual Property (IP) core designed in generic and portable VHDL. XIP8001B has been designed for easy integration with FPGA- and ASIC-based designs, and consequently its design methodology is vendor-agnostic, and the functionality of XIP8001B does not rely on any FPGA manufacturer-specific features. XIP8001B includes the NIST SP 800-90B specified startup tests and online health tests.

The output of the entropy source (the so-called “raw bits”) in XIP8001B have been successfully tested with PractRand, gjrand, TestU01, NIST SP 800-22 statistical test suite and the dieharder test suite. XIP8001B includes a NIST SP 800-90B compliant AES-CBC-MAC -based entropy extractor, thus making XIP8001B suitable for use in a crypto module targeting a FIPS 140-3 certification.

Key features

  • Compact Size: The entire design requires less than 1.7k 6-input LUTs (lookup tables) and 1-2 internal memory blocks [1] (BRAM = Block RAM) in an FPGA implementation.
  • Autonomous Operation: The entropy source used by XIP8001B functions independently from the rest of the FPGA logic; for example no FPGA internal clock signals are required for the entropy source to function.
  • Parameterizability: XIP8001B has a number of parameterizable features, including the width of the dout output, the sizes (width and depth) of the internal buffers, and the threshold values for the health tests.
  • Security Features: XIP8001B has a number of additional security features, including a zeroize function to erase (set to ’0’) all the bits in the internal buffer.
  • Standard Compliance: The core has been designed to comply with NIST SP 800-90B, thus making its use in a crypto module targeting a FIPS 140-2 certification possible.
  • Passing Statistical Tests: The output of the entropy source in XIP8001B passes PractRand, gjrand, TestU01, the NIST SP 800-22 statistical test suite, and the dieharder test suite.

Functionality

The internal block diagram of XIP8001B is depicted in Figure 1. When enabled, the entropy source generates a continuous stream of random bits (the so-called “raw bits”), which are monitored by the NIST SP 800-90B compliant online health tests. The internal “raw bits” are only written to internal buffer if they pass the online health tests. The entropy extractor is based on NIST SP 800-90B compliant AES-CBC-MAC design, whose output is written to the output buffer [2]. The random bits generated by XIP8001B can be read by the external FPGA design on the dout output.


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Block diagram

Figure 1: Internal high-level block diagram of XIP8001B

Figure 1: Internal high-level block diagram of XIP8001B

Footnotes

[1] The memory block consumption depends on the size of the internal and output buffer as well as on the FPGA architecture.

[2] The output buffer is designed as a FIFO with a default word width of 32 bits.


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