Hardware-based security for high-level protection.


RSA Signature Verification IP Core


XIP5012C from Xiphera is a very compact Intellectual Property (IP) core designed for RSA (Rivest-Shamir-Adleman) signature verification. XIP5012C supports all modulus lengths up to 4096 bits, and it can also be used for RSA public key exponentiation. RSA signature verification is used in numerous contemporary security protocols and applications, including TLS 1.3.

XIP5012C has been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of XIP5012C does not rely on any FPGA manufacturer-specific features.

Key features

  • Minimal Resource Requirements: The entire XIP5012C requires less than 280 LUTs (lookup tables) and 2 internal memory blocks (Xilinx® Zynq®-7000) [1].
  • Performance: Despite its small size, XIP5012C can support more than 10 digital signature verification operations per second.
  • Standard Compliance: XIP5012C is compliant with FIPS 186-4.


XIP5012C computes exponentiations with a public exponent, and it supports all modulus sizes up to 4096 bits [2]. The modulus size can also be set to a lower value to speed up the computations.

The public exponent must an odd number and fit into one 32-bit word. Both the modulus size and the exponent can be changed during the operation of XIP5012C by writing new values into registers in XIP5012C.

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Block diagram

Figure 1: Internal high-level block diagram of XIP5012C

Figure 1: Internal high-level block diagram of XIP5012C


[1] The exact number depends on the targeted FPGA architecture.

[2] Upon request, the current upper limit of 4096 bits can be increased. This will have an impact on the FPGA resource utlization.

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