Hardware-based security for high-level protection.

XIP3032H: SHA3-256

Secure Hash Algorithm-3 (256 bit digest) IP Core


XIP3032H from Xiphera is a high-speed Intellectual Property (IP) core implementing the Secure Hash Algorithm-3 with a 256 bits long message digest (hash). The SHA-3 family of hash functions are based on the Keccak sponge function, and their internal structure is different from the SHA-2 family of hash functions which are based on the Merkle-Damgård structure. The hashing speeds achieved with FPGA-based implementations of SHA-3 are faster than those achieved with SHA-2, and consequently SHA-3 hash functions are a strong candidate for applications where the primary goal is to maximimize throughput.

XIP3032H has been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of XIP3032H does not rely on any FPGA manufacturer-specific features.

Key features

  • Performance: Despite its modest size, XIP3032H achieves a throughput in the 10+ Gbps range [1], for example ∼ 22 Gbps in Xilinx® UltraScale+™ MPSoC.
  • Modest Resource Requirements: The entire XIP3032H requires 3.8k ALMs (Adaptive Lookup Modules), and does not require any multipliers, DSPBlocks or internal memory in a typical FPGA implementation.
  • Standard Compliance: XIP3032H is fully compliant with the Secure Hash Algorithm-3 published by the National Institute of Standards and Technology (NIST), and passes the test vectors published by NIST.
  • Byte-orientated 64-bit Interface eases the integration of XIP3032H with other FPGA logic and/or control software.


The main functionality of XIP3032H is to calculate a message digest (also commonly known as a hash value) with a length 256 bits. XIP3032H pads the incoming message into 1088 bits long message blocks [2] as specified in the Secure Hash Algorithm-3, absorbs the message blocks into the 1600 bits long state array, and runs the Keccak algorithm for twenty-four (24) rounds after each message block has been absorbed [3].

After the last incoming message has been received, XIP3032H finalized the message digest calculation, and the resulting message digest is output during consecutive four clock cycles on the 64 bits wide digest output signal.

For more technical and commercial details, including FPGA resources & peak performance as well as ordering instructions, open the full product brief in PDF. Contact us by sending and email to email_career.png, and we’ll get back to you as soon as possible.

Open full product brief

Block diagram

Figure 1: Internal high-level block diagram of XIP3032H

Figure 1: Internal high-level block diagram of XIP3032H


[1] As is typical for sequential hash algorithms, the highest throughput is achieved for long messages.

[2] This is also called the block size or rate of SHA3-256, and can be calculated as 1600 − capacity, where 1600 is the size of the Keccak state array, and capacity is defined as twice the length of the digest (256 bits in the case of SHA3-256).

[3] The total number of clock cycles to process one message block is 25—Keccak for 24 clock cycles and one additional clock cycle for the absorbing phase.

Visit the product family page