Hardware-based security for high-level protection.

XIP3026B: SHA512, SHA384, SHA512/256 AND SHA512/224

Secure Hash Algorithm (SHA512, SHA384, SHA512/256 and SHA512/224) IP Core


Introduction

XIP3026B from Xiphera is a balanced Intellectual Property (IP) core implementing the secure hash algorithms SHA512, SHA384, SHA512/216 and SHA512/224 as specified in the Secure Hash Standard published by the National Institute of Standards and Technology (NIST). The message [1] is parsed and padded into 1024 bits long message blocks, and the resulting message digest (hash value) is either 512, 384, 256 or 224 bits long.

XIP3026B has been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of XIP3026B does not rely on any FPGA manufacturer-specific features.

Key features

  • Compact resource requirements: The entire XIP3026B requires less than 3200 lookup tables (LUTs) (Xilinx® UltraScale+™ MPSoC), and does not require any multipliers, DSPBlocks or internal memory in a typical FPGA implementation.
  • Performance: Despite its compact size, XIP3026B achieves a throughput in the Gbps range [2], for example 2.5+ Gbps in Xilinx® UltraScale+™ MPSoC.
  • Standard Compliance: XIP3026B is fully compliant with the Secure Hash Standard published by the National Institute of Standards and Technology (NIST), and passes the test vectors published by NIST.
  • Byte-orientated 64-bit Interface eases the integration of XIP3026B with other FPGA logic and/or control software.

Functionality

The main functionality of XIP3026B is to calculate a message digest (also commonly known as a hash value) with a length of either 512 bits (SHA512), 384 bits (SHA384), 256 bits (SHA512/256), or 224 bits (SHA512/224). XIP3026B pads and parses the incoming message into 1024 bits long message blocks as specified in the Secure Hash Standard, and adds the length information to the last 64 bits of the last 1024 bits long message block.

After the message digest has been calculated, the result is output during consecutive eight (SHA512), six (SHA384), or four (both SHA512/256 and SHA512/224) clock cycles on the 64 bits wide digest output signal.

After the message digest has been output, the hash algorithm in use for the next message can be controlled by changing the value on the input signal sha_mode.


For more technical and commercial details, including FPGA resources & peak performance as well as ordering instructions, open the full product brief in PDF. Contact us by sending and email to email_career.png, and we’ll get back to you as soon as possible.

Open full product brief

Block diagram

Figure 1: Internal high-level block diagram of XIP3026B

Figure 1: Internal high-level block diagram of XIP3026B

Footnotes

[1] The maximum total message size is 2128 − 1 bits.

[2] As is typical for sequential hash algorithms, the highest throughput is achieved for long messages.


Visit the product family page