XIP3022B from Xiphera is a balanced Intellectual Property (IP) core implementing the secure hash algorithms SHA-224 and SHA-256 as specified in the Secure Hash Standard published by the National Institute of Standards and Technology (NIST). The message  is parsed and padded into 512 bits long message blocks, and the resulting message digest (hash value) is either 256 or 224 bits long.
XIP3022B has been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of XIP3022B does not rely on any FPGA manufacturer-specific features.
The main functionality of XIP3022B is to calculate a message digest (also commonly known as a hash value) with a length of either 256 bits (SHA256) or 224 bits (SHA224). XIP3022B pads and parses the incoming message into 512 bits long message blocks as specified in the Secure Hash Standard, and adds the length information to the last 64 bits of the last 512 bits long message block.
After the message digest has been calculated, the result is output during consecutive eight (SHA256) or seven (SHA224) clock cycles on the 32 bits wide digest output signal. After the message digest has been output, the hash algorithm in use for the next message can be controlled by changing the value on the input signal sha256_or_224.
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Figure 1: Internal high-level block diagram of XIP3022B
 The maximum total message size is 264 − 1 bits.
 As is typical for sequential hash algorithms, the highest throughput is achieved for long messages.
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