Hardware-based security for high-level protection.

XIP1101H: AES128-CTR

Advanced Encryption Standard (128-bit key), Counter Mode IP Core


Introduction

XIP1101H from Xiphera is a high-speed Intellectual Property (IP) core implementing the Advanced Encryption Standard (AES) in Counter Mode (CTR).

The Counter mode of operation effectively turns a block cipher into a stream cipher, and provides a number of advantages from an implementation point of view. These include the ability to use the same key expansion functionality and datapath for both encryption and decryption, and the possibility to parallelize the FPGA-based implementation by unrolling and pipelining.

XIP1101H has been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of XIP1101H does not rely on any FPGA manufacturer-specific features.

Key features

  • Moderate resource requirements: The entire XIP1101H requires less than 13000 Adaptive Lookup Modules (ALMs) (Intel® Cyclone® V), and does not require any multipliers or DSPBlocks [1].
  • Performance: Despite its moderate size, XIP1101H achieves a throughput in the tens of Gbps range, for example 100+ Gbps in Xilinx® UltraScale+™ MPSoC.
  • Standard Compliance: XIP1101H is fully compliant with both the Advanced Encryption Algorithm (AES) standard, as well as with the Counter Mode (CTR) standard.
  • 128-bit Interfaces ease the integration of XIP1101H with other FPGA logic and/or control software.

Functionality

XIP1101H encrypts [2] the incoming 128 bits long plaintext blocks by XORing (exclusive-OR) them with the encrypted successive values of a counter. The counter is initialized with a 128 bits long initialization vector [3], which is then incremented by one after each encryption with the same secret key.

XIP1101H is a high-speed version of the Counter mode of operation, and due to the full unrolling of the AES datapath can output a 128 bits long ciphertext block every clock cycle. The key expansion — which is identical for both encryption and decryption operation — is performed on-the-fly and if the same key is used for successive plaintext blocks does not affect the throughput or latency of XIP1101H.


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Block diagram

Figure 1: Internal high-level block diagram of XIP1101H, encryption mode

Figure 1: Internal high-level block diagram of XIP1101H, encryption mode.

Footnotes

[1] The AES S-boxes can be implemented either in FPGA logic or internal memory blocks depending on the customer’s preference.

[2] The operation is identical in the decryption direction, where the only difference is decrypting ciphertext into plaintext.

[3] The initialization vector consists of a 32 bits long nonce, and a 96 bits long initial value.


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