Hardware-based security for high-level protection.

XIP1101B: AES128-CTR

Advanced Encryption Standard (128-bit key), Counter Mode IP Core


Introduction

XIP1101B from Xiphera is a balanced Intellectual Property (IP) core implementing the Advanced Encryption Standard (AES) in Counter Mode (CTR).

The Counter mode of operation effectively turns a block cipher into a stream cipher, and provides a number of advantages from an implementation point of view. These include the ability to use the same key expansion functionality and datapath for both encryption and decryption, and the possibility to parallelize the FPGA-based implementation by unrolling and pipelining.

XIP1101B has been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of XIP1101B does not rely on any FPGA manufacturer-specific features.

Key features

  • Compact resource requirements: The entire XIP1101B requires less than 1000 Adaptive Lookup Modules (ALMs) (Intel® Cyclone® V), and does not require any multipliers or DSPBlocks [1].
  • Performance: XIP1101B achieves an impressive throughput in the Gbps range, for example 6.55+ Gbps in Xilinx® UltraScale+™ MPSoC.
  • Standard Compliance: XIP1101B is fully compliant with both the Advanced Encryption Algorithm (AES) standard, as well as with the Counter Mode (CTR) standard.
  • 128-bit Interface or 32-bit Interface ease the integration of XIP1101B with other FPGA logic and/or control software.

Functionality

XIP1101B encrypts [2] the incoming 128 bits long plaintext blocks by XORing (exclusive-OR) them with the encrypted successive values of a counter. The counter is initialized with a 128 bits long initialization vector [3], which is then incremented by one after each encryption with the same secret key.

XIP1101B is a balanced version of the Counter mode of operation, and the encryption of a 128 bits long plaintext block takes ten (10) clock cycles. The key expansion —which is identical for both encryption and decryption operation —is performed on-the-fly and does not affect the throughput or latency of XIP1101B.


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Block diagram

Figure 1: Internal high-level block diagram of XIP1101B, encryption mode

Figure 1: Internal high-level block diagram of XIP1101B, encryption mode.

Footnotes

[1] The AES S-boxes can be implemented either in FPGA logic or internal memory blocks depending on the customer’s preference.

[2] The operation is identical in the decryption direction, where the only difference is decrypting ciphertext into plaintext.

[3] The initialization vector consists of a 32 bits long nonce, and a 96 bits long initial value.


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