The first 5G networks have followed a single-vendor model, and telecom operators have had a limited number of suppliers to choose from when deciding where to obtain all the network components.
The O-RAN ALLIANCE was founded in 2018 as a global community of mobile network operators of the Radio Access Network (RAN) industry, and it aims for more intelligent, open, and collaborative mobile networks. The ongoing standardisation work by the O-RAN ALLIANCE for open interfaces between network components – for example, the Open Fronthaul (Open FH) between the Radio Units (RU) and the Distributed Units (DU) – expands the ecosystem and fosters competition and innovations between OEMs.
The open RAN, however, does not only bring benefits, but creates potential security threats. These threats must be identified and proactively addressed in the O-RAN network architecture to support the confidentiality, authenticity, and integrity of messages on the open interfaces. These requirementes also apply for the Precision Time Protocol (PTP) based synchronisation messages on the Open FH.
Addressing the security of synchronisation messages
A well-known security protocol to address the security challenges introduced above is MACsec. As the features of Field Programmable Gate Arrays (FPGA) include low processing latency and high throughput, they are natural candidates for MACsec implementations on Open FH requiring tens of gigabits per second throughput.
Xiphera publishes a white paper, titled ‘Security with timing accuracy: PTP support with MACsec IP core’. “In the white paper, Xiphera introduces a methodology for secure timing synchronisation over Open Fronthaul using Intel® Agilex™ FPGAs”, Tuomo Tarvainen, Xiphera’s System Architect, concludes. “The solution is a combination of Xiphera’s MACsec IP cores and the features of Intel® Agilex™ FPGA transceivers.”
Both the security of Open FH and the timing information accuracy can be accomplished with Xiphera’s MACsec Intellectual Property (IP) cores when implemented on Intel ® Agilex™ FPGAs. “Our implementation methodology enables the highest possible time stamping accuracy which the Intel® Agilex™ FPGA transceivers can support”, Tuomo Tarvainen confirms.
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