AES-XTS
Xiphera’s AES-XTS IP core with a 256-bit key length is a block-based encryption method primarily employed to secure stored data.
AES-XTS IP cores implement the Advanced Encryption Standard (AES) with a 256-bit key in XTS mode. AES-XTS is a block-based encryption method primarily employed to secure data while it is stored, and the IP cores can be used to encrypt data on hard drives and other storage devices. Xiphera’s in-house designed, CAVP-validated AES-XTS IP cores have been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology.
Enhance your security with advanced AES-XTS encryptions for…
Data protection in storage
Memory protection
Data centres
Cloud environments
Key features
- CAVP validated by NIST
- Compliant with NIST standards
- Optional ciphertext stealing supported
- Increased performance with parallel instantiations
- Pure RTL without hidden CPU or software components
- Easy system integration
- Vendor agnostic FPGA/ASIC implementation
Technical specifications
Xiphera’s AES IP cores offer various modes, ensuring performance, flexibility, and robust security.
Balanced AES256-XTS
Product code: XIP1183B
- Several Mbps
- Only ~6 kLUTs
- CAVP validated IP core
High-speed AES256-XTS
Product code: XIP1183H
- 10s of Gbps
- ~33 kLUTs
- CAVP validated IP core
Product brief
Learn more about the key features and functionalities of the AES-XTS IP cores.
Resource sheet
Download the resource sheet to learn more about the FPGA and ASIC resource requirements and performance.
AES-GCM for confidentiality and authenticity
AES-GCM is a widely used cryptographic algorithm for Authenticated Encryption with Associated Data (AEAD) purposes, providing both data confidentiality and authenticity. Xiphera offers AES-GCM cores for both optimal efficiency and high performance.
