Hardware-based digital logic in electronic devices is typically implemented either in Field Programmable Gate Arrays (FPGAs) or as Application Specific Integrated Circuits (ASICs). They have obvious differences, but also similarities. The main difference is already implied in the word FPGA, namely (re)programmability, and consequently an FPGA can be used for multiple applications, whereas an ASIC is designed for a specific application and cannot be reprogrammed.
The reprogrammability of an FPGA comes with a price, and this is due to the fact that their structure is typically – but not exclusively – based on Static Random Access Memory (SRAM) -based lookup tables (LUTs) and reprogrammable internal routing architecture. As ASICs are not based on reprogrammable LUTs and routing but instead implement the required digital logic directly in silicon and connect them with fixed wiring, they have a smaller silicon area at a corresponding process node and therefore their unit cost is significantly lower compared to FPGAs. ASICs also typically have better performance and lower power consumption.
However, despite their higher unit cost, the use of FPGAs is economically justified for small-to-medium sized volume production. This is because the design and manufacturing of an ASIC includes more expensive Electronic Design Automation (EDA) tool licensing costs, and most importantly the Non-Recurring Engineering (NRE) cost of an ASIC tapeout makes an ASIC attractive economically only after a certain volume threshold has been reached. Importantly, there may also be more than one required tapeout and associated NRE cost as the first ASIC may have bugs which need to be fixed; this also will negatively affect the time-to-market.
FPGAs and ASICs also have a lot of similarities, including the first steps of their design process. The design is first described textually at the Register Transfer Level (RTL) in either VHDL or (System)Verilog – both of which Xiphera supports – and then synthesised into a netlist.
Ideally, the RTL codebase is identical for both FPGAs and ASICs, and most of Xiphera’s Intellectual Property (IP) cores do not require any changes when targeting FPGAs or ASICs (the small changes required for certain IP cores relate to the implementation of memory blocks, which may depend on the standard cell library of the chosen ASIC process). This also enables our customers to build their prototypes and perhaps a small pre-production run with FPGAs before switching to ASICs for full volume production.
Another similarity is the ever-increasing design complexity of modern FPGAs and ASICs – it makes sense for companies to focus on their core competencies. Instead of trying to design every single piece of digital logic on their own, it often makes perfect sense to use third-party IP cores for specific expert functionality, such as cryptography and security protocols.
Xiphera offers proven security for both FPGAs and ASICs
When Xiphera was founded in 2017, the cryptographic IP core portfolio was initially designed to support FPGAs for a number of reasons, including personal familiarity with the technology and Xiphera’s partnerships with leading FPGA companies.
However, Xiphera’s cryptographic IP cores and security protocols have supported ASIC designs for a considerable period of time, and the first ASIC which includes Xiphera’s cryptographic IP core has returned from a silicon foundry. Xiphera’s cryptographic IP cores are fully digital and therefore support in principle all ASIC process nodes as the RTL includes no process-specific dependencies.
In conclusion, our customers’ choice between using an FPGA or ASIC depends on the specific needs of the project and the stage of development, and Xiphera is happy to support either one of these mainstream technologies with our proven cryptographic security solutions.
Xiphera offers ASIC product briefs (Resource requirements start from a few thousand gates) for the following IP cores:
- AES (256-bit key), Counter Mode IP core (download product brief)
- AES (256-bit key), Galois Counter Mode IP core, balanced version (download product brief)
- AES (256-bit key), Galois Counter Mode IP core, high-speed version (download product brief)
- AES (256-bit key), ECB CBC, OFB, CFB, and CTR Mode of Operation (download product brief)
- AES (256-bit key), XTS mode IP core (download product brief)
- Balanced IP core for ChaCha20-Poly1305 Authenticated Encryption (download product brief)
- Ascon, Lightweight cryptographic suite for AEAD and hashing (download product brief)
- SHA-3, High-speed Versatile core for SHA-3-224/256/384/512 and (c)SHAKE-128/256 (download product brief)
- HKDF/HMAC/SHA-256 IP core with extended functionalities (download product brief)
- HKDF/HMAC/SHA-384 IP core with extended functionalities (download product brief)
- HKDF/HMAC/SHA-512 IP core with extended functionalities (download product brief)
- Compact ECC IP cores supporting ECDH and ECDSA on NIST P-256/P-384 (download product brief)
- RSA Signature Verification IP core (download product brief)
- Balanced Post-Quantum Key Encapsulation IP core (download product brief)
- True Random Number Generator IP core (download product brief)
Find all ASIC and FPGA specific product briefs at the product pages for the individual IP cores, product family pages, or the Product Catalogue page.