Xiphera's product portfolio consist of standardized and efficient cryptographic Intellectual Property (IP) cores, which enable the design of an embedded system meeting the cybersecurity requirements for confidentiality, integrity, authenticity, and non-repudiability.
The majority of current implementations of cryptographic algorithms are based on software running on a processor, but this approach may suffer from underlying processor bugs and features, operating system weaknesses, third party software library weaknesses, and performance concerns.
Xiphera's design philosophy targets a direct implementation of the cryptographic algorithms in hardware, and therefore the cryptographic IP cores have been designed for Field Programmable Gate Arrays (FPGAs) as the target technology.
Using FPGA as the target technology for cryptography combines efficiency with first grade security. This is based on the ability to have detailed control — down to level of individual bits and clock cycles — of the implementation of a cryptographic algorithm.
Xiphera's primary target technology is FPGA, but there are no technical obstacles for porting the IP cores to an ASIC (Application Specific Integrated Circuit) design, as the cores are written in device-independent and portable HDL (Hardware Description Language).
Please request further details from firstname.lastname@example.org (Product Brief or more detailed Data Sheet for a particular FPGA family).
Three Product Briefs are available as examples.
All Xiphera IP cores listed below are fully constant time implementations and offer high level of protection against common side-channel attacks.
The letter (B, C, or H) at the end of the IP core is interpreted as follows:
All IP cores are shipped with extensive test bench and documentation. The default external interface of Xiphera IP cores is AMBA™ AXI4 (Advanced eXtensible Interface 4), but on request the external interface can be tailored to the customer's needs.
The following IP cores implement the AES block cipher in Counter (CTR), Galois Counter (GCM), or Cipher Block Chaining (CBC) mode of operation. All of Xiphera's AES IP cores are available with support for standardized key lengths of 128, 192, and 256 bits.
The following IP cores implement the SHA-2 standard with standardized digest lengths (224, 256, 384 or 512 bits).
The following IP cores implement the SHA-3 standard with standardized digest lengths (224, 256, 384 or 512 bits).
The following IP cores implement the two XOF's (Extendable Output Functions) defined in the SHA-3 standard.
All SHA-3 IP cores comply with FIPS 202.
The following IP cores implement elliptic curve cryptography on Curve25519
Xiphera offer pre-packaged solutions incorporating a number of individual cryptographic IP cores and the associated control logic.
Example solutions include
Please request further details from email@example.com.