Security with FPGAs
Xiphera's product portfolio consist of standardized and efficient cryptographic Intellectual Property (IP) cores, which enable the design of an embedded system meeting the cybersecurity requirements for confidentiality, integrity, authenticity, and non-repudiability.
The majority of current implementations of cryptographic algorithms are based on software running on a processor, but this approach may suffer from underlying processor bugs and features, operating system weaknesses, third party software library weaknesses, and performance concerns.
Xiphera's design philosophy targets a direct implementation of the cryptographic algorithms in hardware, and therefore the cryptographic IP cores have been designed for Field Programmable Gate Arrays (FPGAs) as the target technology.
Using FPGA as the target technology for cryptography combines efficiency with first grade security. This is based on the ability to have detailed control — down to level of individual bits and clock cycles — of the implementation of a cryptographic algorithm.
Xiphera's primary target technology is FPGA, but there are no technical obstacles for porting the IP cores to an ASIC (Application Specific Integrated Circuit) design, as the cores are written in device-independent and portable HDL (Hardware Description Language).
Xiphera IP cores are fully constant time implementations and offer high level of protection against common side-channel attacks.
The letter (B, C, or H) at the end of the IP core is interpreted as follows:
- B = Balanced, optimised for both performance and low FPGA resource usage
- C = Compact, optimised for low FPGA resource usage
- H = High-Speed, optimised for high performance
All IP cores are shipped with extensive test bench and documentation.